module dequeueSpecialUnit (
    input wire clk,
    input wire rst,
    input wire [15:0] dequeue_vld_in,
    input wire [15:0] dequeue_value_in [0:15],
    output reg [15:0] dequeue_vld_out,
    output reg [9:0] dequeue_value_out [0:15]
);
    integer i;

    always @(posedge clk) begin
        if (rst) begin
            dequeue_vld_out <= 16'h0000;
            for (i=0; i<16; i=i+1) begin
                dequeue_value_out[i] <= 0;
            end
        end
        else begin
            for (i=0; i<16; i=i+1) begin
                if (dequeue_vld_in[i]) begin
                    //是发送到专用RAM的请求
                    if (dequeue_value_in[i][15:10] < 16) begin
                        dequeue_vld_out[i] <= 1'b1;
                        dequeue_value_out[i] <= dequeue_value_in[i][9:0];
                    end
                    else begin
                        dequeue_vld_out[i] <= 1'b0;
                    end
                end
                else begin
                    dequeue_vld_out[i] <= 1'b0;
                end
            end
        end
    end
    
endmodule